Fac/Staff profile

Riadul
Islam, Ph.D.

Assistant Professor, Electrical and Computer Engineering
ECE Faculty
313-583-6590
236 CIS
4901 Evergreen
Dearborn, MI 48128

Research Areas:

Biography and Education

Riadul Islam is a tenure track Assistant Professor in the Department of Electrical & Computer Engineering at University of Michigan (UM) Dearborn. In his Ph.D. dissertation work at UCSC, Dr. Riadul has designed the first current-pulsed flip-flop/register that resulted first ever one-to-many current-mode clock distribution networks for high-performance microprocessors. From 2007 to 2009, he worked as a full-time faculty in the Department of Electrical and Electronic Engineering of the University of Asia Pacific, Dhaka, Bangladesh. He is a member of the IEEE, IEEE Circuits and Systems (CAS) society.

Education

Ph.D., Computer Engineering, University of California Santa Cruz

M.A.Sc., Electrical and Computer Engineering, Concordia University

B.Sc., Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology (BUET)

Teaching and Research

Selected Publications

Patents

1. M. Guthaus and R. Islam, Current-mode clock distribution. US Patent Grant, 9,787,293, October 2017.

Journals

  1. R. Islam, `High-Speed On-Chip Signaling: Voltage or Current-Mode? ,’ accepted in IETE Transactions on Journal of Research (TIJR), Volume:, Issue:, October, 2018.
  2. R. Islam, `Negative Capacitance Clock Distribution ,’ accepted in IEEE Transactions on Emerging Topics in Computing (TETC), Volume:, Issue:, September, 2018.
  3. R. Islam and M. Guthaus, `HCDN: Hybrid-Mode Clock Distribution Networks,’ IEEE Transactions on Circuits and Systems I (TCAS-I), Volume:, Issue:, August, 2018.
  4. R. Islam, H. Fahmy, P. Lin and M. Guthaus, `DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis,’ IEEE Transactions on VLSI Systems (TVLSI), Volume: 26, Issue: 10, October 2018.
  5. R. Islam, `Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops,’ Springer Nature Journal of Electronic Testing: Theory and Applications (JETTA), Volume: 34, Issue: 4, June 2018.
  6. R. Islam and M. Guthaus, `CMCS: Current-Mode Clock Synthesis,’ IEEE Transactions on VLSI Systems (TVLSI), Volume: 25, Issue: 3, March 2017.
  7. R. Islam and M. Guthaus, `Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop,’ IEEE Transactions on Circuits and Systems I (TCAS-I), Volume: 62, Issue: 4, March 2015.

Conferences and Presentations

  1. R. Islam and M. Guthaus, `Low-Jitter Hybrid-Mode Clock Distribution Networks,’ Design Automation Conference (DAC), WIP session, San Francisco, CA, USA, June 2018.
  2. R. Islam and M. Guthaus, `CMCS: Current-Mode Clock Synthesis,’ Design Automation Conference (DAC), WIP session, Austin, Tx, USA, June 2016. Design Automation Conference (DAC), WIP session, Austin, Tx, USA, June 2016.
  3. R. Islam, H. Fahmy, P. Lin and M. Guthaus, `Dierential Current-Mode Clock Distribution,’ IEEE Midwest Symposium on Circuits and Systems (MWSCAS), Fort Collins, USA, August 25, 2015.
  4. P. Lin, H. Fahmy, R. Islam and M. Guthaus, `LC Resonant Clock Resource Minimization using Compensation Capacitance,’ IEEE International Symposium on Circuits and Systems (ISCAS), Portugal, May 24-27, 2015.
  5. H. Fahmy, P. Lin, R. Islam and M. Guthaus, `Switched Capacitor Quasi Adiabatic Clock,’ IEEE International Symposium on Circuits and Systems (ISCAS), Portugal, May 24-27, 2015.
  6. R. Islam and M. Guthaus, `Current-Mode Clock Distribution,’ IEEE International Symposium on Circuits and Systems (ISCAS), Australia, June 1-5, 2014.
  7. S. E. Esmaeili, R. Islam, A. J. Al-khalili, and G. E. R. Cowan, `Dual-Edge Triggered Sense Amplier Flip- Flop Utilizing an Improved Scheme to Reduce Area, Power, and Complexity,’ IEEE International Conference on Electronics Circuits and Systems (ICECS), Seville, Spain, December 09-12, 2012.
  8. R. Islam, `A Highly Reliable SEU Hardened Latch and High Performance SEU Hardened Flip-Flop,’ International Symposium on Quality Electronic Design (ISQED), California, USA, March 19-21, 2012.
  9. R. Islam, S. E. Esmaeili, and T. Islam, `A High Performance Clocked Precharge SEU Hardened Flip- Flop,’ IEEE International Conference on ASIC (ASICON), Xiamen, China, October 25-28, 2011.
  10. S. M. Jahinuzzaman and R. Islam, `TSPC-DICE: A Single Phase Clock High Performance SEU Hardened Flip-Flop,’ IEEE Midwest Symposium on Circuits and Systems (MWSCAS), Seattle, USA, August 1-4, 2010.
 

Awards and Recognition

-2014 IEEE International Symposium on Circuits and Systems (ISCAS) Student Travel Award, Melbourne,
Australia.

· Richard Newton Young Fellow award, 2013 Design Automation Conference (DAC), Austin, USA.
· 2012-2013 UCSC Regents Fellowship, USA.

· Partial Tuition Graduate Scholarship for Int. Students, (5–Terms), Concordia University, 2009-2011, Canada.

· 2002-2007 Technical Scholarship, Bangladesh University of Engineering and Technology, Bangladesh.
Publications

History

Member for
1 year 9 months
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